Datasheet Details
| Part number | MT9046 |
|---|---|
| Manufacturer | Zarlink Semiconductor |
| File Size | 508.51 KB |
| Description | T1/E1 System Synchronizer with Holdover |
| Datasheet |
 MT9046 Datasheet
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General Description
The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links.
Key Features
- Supports AT&T TR62411 and Bellcore GR-1244CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accuracy of 0.2 PPM Holdover indication Attenuates wander from 1.9 Hz Fast.