MT9042C
Overview
The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference.
- Meets jitter requirements for: AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces; and for ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 for E1 interfaces Provides C1.5, C3, C2, C4, C8 and C16 output clock signals Provides 8kHz ST-BUS framing signals Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals Accepts reference inputs from two independent sources Provides bit error free reference switching meets phase slope and MTIE requirements Operates in either Normal, Holdover and Freerun modes
