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MT9040 Datasheet T1/e1 Synchronizer

Manufacturer: Zarlink Semiconductor

Overview: MT9040 T1/E1 Synchronizer Data Sheet.

General Description

The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links.

• • • • Applications • • Synchronization and timing control for multitrunk T1 and E1 systems ST-BUS clock and frame pulse source OSCi OSCo FLOCK LOCK VDD VSS Master Clock TCK TDI TMS TRST TDO IEEE 1149.1a DPLL Output Interface Circuit Input Impairment Monitor REF C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP Control State Machine Feedback Frequency Select MUX MS RST IM FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No.

5,602,884, UK Patent No.

Key Features

  • Supports AT&T TR62411 and Bellcore GR-1244CORE and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 different styles of 8 KHz framing pulses Attenuates wander from 1.9Hz Fast lock mode JTAG Boundary Scan The MT9040 g.

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MT9040 Distributor