Overview: SP5659
2·7GHz I2C Bus Low Phase Noise Synthesiser Preliminary Information
Supersedes March 1996 version, DS4206-1.8 DS4296 - 2.0 June 1998 The SP5659 is a single chip frequency synthesiser designed for tuning systems up to 2·7GHz. The RF preamplifier drives a divide-by two prescaler which can be disabled for applications up to 2GHz, allowing direct interfacing with the programmable divider, resulting in a step size equal to the parison frequency. For applications up to 2·7GHz the divide-by two is enabled to give a step size of twice the parison frequency. The parison frequency is obtained either from an onchip crystal controlled oscillator or from an external source. The oscillator frequency FREF or the parison frequency FP may be switched to the REF/P output; this feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see Fig. 5). The synthesiser is controlled via an I 2C bus and responds to one of four programmable addresses which are selected by applying a specific voltage to the Address input. This feature enables two or more synthesisers to be used in a system. The SP5659 contains four switching ports, P0-P3 and a 5-level ADC, the output of which can be read via the I 2C bus. The SP5659 also contains a varactor line disable and charge pump disable facility. CHARGE PUMP CRYSTAL REF/P ADDRESS SDA SCL PORT P3 PORT P2 1 2 3 4 5 6 7 8 16 15 14 13 DRIVE VEE RF INPUT RF INPUT VCC ADC PORT P0 PORT P1 SP5659 12 11 10 9 MP16
Fig. 1 Pin connections – top view s ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1) s Pin patible with SP5658
(1) Normal ESD handling precautions should be observed.
