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SP8400 - Very Low Phase Noise Synthesiser Divider

General Description

synthesiser divider The divider is based on a divide by 8/9 modulus prescaler, and a 12 stage control counter.

N division ratio of 64 (56 for general division), and a maximum division ratio of 4103.

The inputs to the control counter are TTL/CMOS compatible.

Key Features

  • I Very low Phase Noise (Typically -156dBc/Hz at 1kHz offset) I Supply Voltage 5V M2 M1 M0 VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V GND A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 M3 M4 M5 M6 M7 M8 N/C OUTPUT OUTPUT N/C VCC +5V N/C A2 A1.

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Datasheet Details

Part number SP8400
Manufacturer Zarlink Semiconductor
File Size 409.42 KB
Description Very Low Phase Noise Synthesiser Divider
Datasheet download datasheet SP8400 Datasheet

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Full PDF Text Transcription (Reference)

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www.DataSheet4U.com SP8400 Very Low Phase Noise Synthesiser Divider September 2005 The SP8400 is a very low phase noise programmable divider which is based on a divide by 8/9 dual modulus prescaler and a 12 stage control counter. This gives a minimum division ratio of 56 (64 for fractional - N synthesis applications), and a maximum division ratio of 4103. Special circuit techniques have been used to reduce the phase noise considerably below that produced by standard dividers.The data inputs are CMOS or TTL compatible. The SP8400 is packaged in a 28 pin plastic SO package.