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M2V12D20TP-75 - 512M Double Data Rate Synchronous DRAM

Download the M2V12D20TP-75 datasheet PDF. This datasheet also covers the M2V variant, as both devices belong to the same 512m double data rate synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Key Features

  • - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and data mask are referenced to both edges of DQS - 4 bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequ.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M2V-12D.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Mitsubishi Electric

Part Number Description
M2V12D20TP-75L 512M Double Data Rate Synchronous DRAM
M2V12D20TP-10 512M Double Data Rate Synchronous DRAM
M2V12D20TP-10L 512M Double Data Rate Synchronous DRAM
M2V12D20TP 512M Double Data Rate Synchronous DRAM
M2V12D30TP 512M Double Data Rate Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM DESCRIPTION M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S12D20/30TP achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems. FEATURES - Vdd=Vddq=2.5V+0.