M2V64S20BTP-10L - 64M bit Synchronous DRAM

This page provides the datasheet information for the M2V64S20BTP-10L, a member of the M2V64S20BTP-7 64M bit Synchronous DRAM family.

Product Overview

Mitsubishi

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Datasheet Details

Part number	M2V64S20BTP-10L
Manufacturer	Mitsubishi
File Size	741.74 KB
Description	64M bit Synchronous DRAM
Datasheet	M2V64S20BTP-10L Datasheet
Additional preview pages of the M2V64S20BTP-10L datasheet.

M2V64S20BTP-10L Product details

Description

The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface.

All inputs and outputs are referenced to the rising edge of CLK.

Features

- Single 3.3v ± 0.3v power supply - Clock frequency 125MHz /100MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/Full Page (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Burst Write / Single Write (programmable) - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycle.

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Published: Mar 7, 2016 |