M5M4V64S20ATP-10L Datasheet PDF - Mitsubishi 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM Specs

M5M4V64S20ATP-10L - 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

This page provides the datasheet information for the M5M4V64S20ATP-10L, a member of the M5M 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM family.

Datasheet Summary

Description

The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface.

All inputs and outputs are referenced to the rising edge of CLK.

The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.

Features

- Single 3.3v±0.3v power supply - Clock frequency 125MHz /100MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/Full Page (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Burst Write / Single Write (programmable) - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles.

Datasheet Details

Part number	M5M4V64S20ATP-10L
Manufacturer	Mitsubishi
File Size	1.13 MB
Description	64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Datasheet	M5M4V64S20ATP-10L Datasheet
Additional preview pages of the M5M4V64S20ATP-10L datasheet.

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Full PDF Text Transcription

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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar98 M5M4V64S20ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM Some of contents are subject to change without notice. DESCRIPTION The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.

Published: Apr 26, 2005 |