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M5M4V64S20ATP-12 - 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

Download the M5M4V64S20ATP-12 datasheet PDF. This datasheet also covers the M5M variant, as both devices belong to the same 64m (4-bank x 4194304-word x 4-bit) synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface.

All inputs and outputs are referenced to the rising edge of CLK.

The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.

Key Features

  • - Single 3.3v±0.3v power supply - Clock frequency 125MHz / 100MHz / 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A9 - LVTTL Interfac.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M5M-4V6.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Mitsubishi Electric

Part Number Description
M5M4V64S20ATP-10 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-10L 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8A 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S20ATP-8L 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SDRAM (Rev.0.2) Jan'97 Preliminary MITSUBISHI LSIs M5M4V64S20ATP-8, -10, -12 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.