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M5M4V64S20ATP-8 - 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

This page provides the datasheet information for the M5M4V64S20ATP-8, a member of the M5M 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM family.

Datasheet Summary

Description

The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface.

All inputs and outputs are referenced to the rising edge of CLK.

The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.

Features

  • - Single 3.3v±0.3v power supply - Clock frequency 125MHz / 100MHz / 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A9 - LVTTL Interfac.

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Datasheet preview – M5M4V64S20ATP-8

Datasheet Details

Part number M5M4V64S20ATP-8
Manufacturer Mitsubishi
File Size 1.07 MB
Description 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Datasheet download datasheet M5M4V64S20ATP-8 Datasheet
Additional preview pages of the M5M4V64S20ATP-8 datasheet.

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Full PDF Text Transcription

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SDRAM (Rev.0.2) Jan'97 Preliminary MITSUBISHI LSIs M5M4V64S20ATP-8, -10, -12 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
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