Datasheet4U Logo Datasheet4U.com

M5M5Y5636TG-20 - 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

General Description

The M5M5Y5636TG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Key Features

  • Fully registered inputs and outputs for pipelined operation.
  • Fast clock speed: 250, 225, and 200 MHz.
  • Fast access time: 2.6, 2.8, 3.2 ns.
  • Single 1.8V +150/-100mV power supply VDD.
  • Separate VDDQ for 1.8V I/O.
  • Individual byte write (BWa# - BWd#) controls may be tied LOW.
  • Single Read/Write control pin (W#).
  • Echo Clock outputs track data output drivers.
  • ZQ mode pin for user-selectable output drive strength.
  • 2.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
M5M51008FP CMOS Static RAM Mitsubishi Electric
M5M51008P 1M-Bit CMOS Static RAM Mitsubishi Electric
M5M5117FP 16K-Bit CMOS Static RAM Mitsubishi Electric
M5M5256BP 256K-Bit CMOS Sraric RAM Mitsubishi Electric
M5M5256DKP 262144-Bit CMOS Static RAM Mitsubishi Electric

Other Datasheets by Mitsubishi Electric

Part Number Description
M5M5Y5636TG-22 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
M5M5Y5636TG-25 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
M5M5Y5672TG-20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
M5M5Y5672TG-22 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
M5M5Y5672TG-25 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
2001.June Rev.0.0 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5636TG – 25,22,20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM DESCRIPTION The M5M5Y5636TG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5Y5636TG operates on a single 1.8V power supply and are 1.8V CMOS compatible. FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition.