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M5M5Y5672TG-22 - 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

General Description

The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Key Features

  • Fully registered inputs and outputs for pipelined operation.
  • Fast clock speed: 250, 225, and 200 MHz.
  • Fast access time: 2.6, 2.8, 3.2 ns.
  • Single 1.8V +150/-100mV power supply VDD.
  • Separate VDDQ for 1.8V I/O.
  • Individual byte write (BWa# - BWh#) controls may be tied LOW.
  • Single Read/Write control pin (W#).
  • Echo Clock outputs track data output drivers.
  • ZQ mode pin for user-selectable output drive strength.
  • 2.

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Other Datasheets by Mitsubishi Electric

Part Number Description
M5M5Y5672TG-20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
M5M5Y5672TG-25 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
M5M5Y5636TG-20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
M5M5Y5636TG-22 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
M5M5Y5636TG-25 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#, BWh#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write operations are controlled by the eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry.