M5M5Y5672TG-25 Overview
The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability.
M5M5Y5672TG-25 Key Features
- Fully registered inputs and outputs for pipelined operation
- Fast clock speed: 250, 225, and 200 MHz
- Fast access time: 2.6, 2.8, 3.2 ns
- Single 1.8V +150/-100mV power supply VDD
- Separate VDDQ for 1.8V I/O
- Individual byte write (BWa#
- BWh#) controls may be tied LOW
- Single Read/Write control pin (W#)
- Echo Clock outputs track data output drivers
- ZQ mode pin for user-selectable output drive strength
M5M5Y5672TG-25 Applications
- Fully registered inputs and outputs for pipelined operation