V58C2256 Overview
The V58C2256(804/404/164)S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are ocurring on both edges of DQS.
V58C2256 Key Features
- High speed data transfer rates with system frequency up to 166 MHz
- Data Mask for Write Control
- Four Banks controlled by BA0 & BA1
- Programmable CAS Latency: 2, 2.5
- Programmable Wrap Sequence: Sequential or Interleave
- Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type
- Automatic and Controlled Precharge mand
- Power Down Mode
- Auto Refresh and Self Refresh
- Refresh Interval: 8192 cycles/64 ms
