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DSP56651 - INTEGRATED CELLULAR BASEBAND PROCESSOR

Description

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Features

  • DSP56651 Features RISC M.
  • CORE MCU.
  • 32-bit load/store RISC architecture.
  • Fixed 16-bit instruction length.
  • 16-entry 32-bit general-purpose register file.
  • 32-bit internal address and data buses.
  • Efficient four-stage, fully interlocked execution pipeline.
  • Single-cycle execution for most instructions, two cycles for branches and memory accesses.
  • Special branch, byte, and bit manipulation instructions.
  • Support for byte,.

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Datasheet preview – DSP56651

Datasheet Details

Part number DSP56651
Manufacturer Motorola
File Size 1.25 MB
Description INTEGRATED CELLULAR BASEBAND PROCESSOR
Datasheet download datasheet DSP56651 Datasheet
Additional preview pages of the DSP56651 datasheet.

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Full PDF Text Transcription

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MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56651/D Rev 0, 6/98 Advance Information DSP56651 INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC Motorola designed the RAM-based DSP56651 emulation device to support the rigorous demands of developing applications for the cellular subscriber market. The high level of on-chip integration in the DSP56651 and its volume production companion device DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low-power consumption and cost-effective system performance.
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