MC100ELT26
features
. The VBB output allows the ELT26 to also be used in a single-ended input mode. In this mode the VBB output is tied to the IN input for a non-inverting buffer or the IN input for an inverting buffer. If used the VBB pin should be bypassed to ground via a 0.01µF capacitor. The ELT26 is available in both ECL standards: the 10ELT is patible with positive MECL 10H logic levels while the 100ELT is patible with positive ECL 100K logic levels.
MC10ELT26 MC100ELT26
8 1
D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05
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3.5ns Typical Propagation Delay <500ps Typical Output to Output Skew Differential PECL Inputs Small Outline SOIC Package 24m A TTL Outputs Flow Through Pinouts
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
NC 1
PIN Qn D VCC VBB GND
FUNCTION TTL Outputs Diff PECL Input +5.0V Supply Reference Output Ground
2 TTL
Q0
Q1
PECL
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