This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | MC68HC68R2 |
|---|---|
| Datasheet | MC68HC68R2 MC68HC68R1 Datasheet (PDF) |
| File Size | 81.25 KB |
| Manufacturer | Motorola Semiconductor (now NXP Semiconductors) |
| Description | 8-BIT SERIAL STATIC RAMs |
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CHIP ENABLE AND SLAVE SELECT (CE AND SS) A high level on the CE pin, coincident with a low level on the SS pin, is required for the RAM serial interface logic to bee enabled. The device is held in the reset state if either CE is low or SS is high. SERIAL CLOCK (SCK) This clock input is used to synchronously latch data in and shift data out of the RAM chip.
See all Motorola Semiconductor (now NXP Semiconductors) datasheets
| Part Number | Description |
|---|---|
| MC68HC68R1 | 8-BIT SERIAL STATIC RAMs |
| MC68HC68T1 | Straight 1-Row BergStik II Headers |
| MC68HC000 | Low Power HCMOS 16-/32-Bit Microprocessor |
| MC68HC04J2 | 8-Bit Microcontroller |
| MC68HC04J3 | 8-Bit Microcontroller |
| MC68HC04P2 | 8-BIT HCMOS MICROCOMPUTER |
| MC68HC04P3 | 8-BIT HCMOS MICROCOMPUTER |
| MC68HC05 | 8-Bit Microcontroller Unit |
| MC68HC05B16 | HCMOS Microcomputer |
| MC68HC05B32 | HCMOS Microcomputer |
