MC74HC390 Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 4-Stage Binary Ripple Counter with ÷ 2 and ÷ 5 Sections High- Performance Silicon- Gate CMOS The MC54/74HC390 is identical in pinout to the LS390. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LSTTL outputs. This device consists of two independent 4- bit counters, each posed of a divide- by- two and a divide- by- five section. The divide- by- two and divide- by- five counters have separate clock inputs, and can be cascaded to implement various binations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter. Flip- flops internal to the counters are triggered by high- to- low transitions of the clock input. A separate, asynchronous reset is provided for each 4- bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390. - - - - - - Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In pliance with the Requirements Defined by JEDEC Standard No 7A - Chip plexity: 244 FETs or 61 Equivalent Gates MC54/74HC390 16 1 J SUFFIX CERAMIC PACKAGE CASE 620- 10 16 1 LOGIC DIAGRAM CLOCK A 1, 15 CLOCK B w 4, 12 2, 14 w .D w ÷2 COUNTER ÷5 COUNTER 3, 13 t a S a e h t e U 4 .c 1 2 3 4 5 6 7 8 m o N SUFFIX PLASTIC PACKAGE CASE 648- 08 D SUFFIX SOIC PACKAGE CASE 751B- 05 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC PIN ASSIGNMENT CLOCK Aa RESET a QAa CLOCK Ba QBa QCa QDa GND 16 15 14 13 12 11 10 9 VCC CLOCK Ab RESET b QAb CLOCK Bb QBb QCb QDb 5,...