MC74HC393A Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Dual 4-Stage Binary Ripple Counter High- Performance Silicon- Gate CMOS The MC54/74HC393A is identical in pinout to the LS393. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LSTTL outputs. This device consists of two independent 4- bit binary ripple counters with parallel outputs from each counter stage. A ÷ 256 counter can be obtained by cascading the two binary counters. Internal flip- flops are triggered by high- to- low transitions of the clock input. Reset for the counters is asynchronous and active- high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the HC393A. - - - - - - Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In pliance with the Requirements Defined by JEDEC Standard No. 7A - Chip plexity: 236 FETs or 59 Equivalent Gates MC54/74HC393A 14 1 J SUFFIX CERAMIC PACKAGE CASE 632- 08 14 1 14 1 LOGIC DIAGRAM CLOCK 1, 13 BINARY COUNTER RESET 2, 12 w w .D w 3, 11 5, 9 6, 8 4, 10 t a Q1 Q2 Q3 Q4 S a e h t e U 4 14 1 .c m o N SUFFIX PLASTIC PACKAGE CASE 646- 06 D SUFFIX SOIC PACKAGE CASE 751A- 03 DT SUFFIX TSSOP PACKAGE CASE 948G- 01 ORDERING INFORMATION Ceramic Plastic SOIC TSSOP MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT PIN ASSIGNMENT CLOCK a RESET a Q1a Q2a Q3a Q4a GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC CLOCK b RESET b Q1b Q2b Q3b Q4b PIN 14 = VCC PIN 7 = GND FUNCTION TABLE Inputs Clock X H L Reset H L L L L Outputs L No Change No Change No Change Advance to Next State This document contains information on a product under development. Motorola reserves the right to change or...