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MCM63F837 - (MCM63F837 / MCM63F919) 256K x 36 and 512K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address.

Used to initiate a READ, WRITE, or chip deselect.

Key Features

  • ables output buffers (DQx pins). High.
  • DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not regist.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM63F819K (MCM63F737K / MCM63F819K) 128K x 36 and 256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM63F733A 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM63F737K (MCM63F737K / MCM63F819K) 128K x 36 and 256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM63F919 256K x 36 and 512K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM6323A 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63F837/D Product Preview 256K x 36 and 512K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM63F837 and MCM63F919 are 8M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. The MCM63F837 (organized as 256K words by 36 bits) and the MCM63F919 (organized as 512K words by 18 bits) are fabricated in Motorola’s high performance silicon gate CMOS technology. Synchronous design allows precise cycle control with the use of an external clock (K).