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MCM64AF32 - 256K Asynchronous Secondary Cache Module for Pentium

General Description

160 Lead Card Edge Pin Locations 21, 22, 23, 24, 28, 29, 102, 103, 104, 106, 108, 109, 110 9, 89 16, 97 98 11, 12, 13, 14, 92, 93, 94, 96 8 91 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120,

Key Features

  • VCC + 2.0 V ac (pulse width ≤ 10% tAVAV (min)).
  • For Tag, VIL (min) =.
  • 0.5 V dc; VIL (min) =.
  • 2.0 V ac (pulse width ≤ 20 ns). For Data, VIL (min) =.
  • 0.5 V dc; VIL (min) =.
  • 2.0 V ac (pulse width ≤ 10% tAVAV (min)). DC.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM64AF32/D Product Preview MCM64AF32 160–LEAD CARD EDGE CASE TBD* TOP VIEW 1 256K Asynchronous Secondary Cache Module for Pentium™ The MCM64AF32 is designed to provide 256K of asynchronous L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The module is configured as 32K x 64 bits in a 160 pin card edge connector. The module uses eight Motorola 3.3 V 32K x 8 FSRAMs for the cache memory, one Motorola 5 V 32K x 8 FSRAM for the tag RAM, and an upper order address latch. Eight write enables are provided for byte write control. PD0–PD4 identify density and functionality.