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MCM69L736A - 4M Late Write HSTL

General Description

PBGA Pin Locations 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T 4K 4L 4M 5L, 5G, 3G, 3L (a), (b), (c), (d) 4E 4F 2U 3U 4U 5U 4D 7T (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2

Key Features

  • >.
  • Typical.
  • 7.5.
  • 300 390 190 160 140 TBD Typical.
  • 8.5.
  • 290 380 190 160 140 TBD Typical.
  • 9.5.
  • 270 360 190 160 140 TBD Typical.
  • 10.5.
  • 260 350 190 160 140 TBD Max 1.1 3.6 1.6 450 560 250 250 230 TBD Unit V V V mA.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69L736A/D Advance Information 4M Late Write HSTL The MCM69L736A/818A is a 4M synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69L818A (organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K words by 36 bits) are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK, all addresses, write enables, and synchronous selects are registered.