MCM69Q536 Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69Q536/D Advance Information 32K x 36 Bit Synchronous Separate I/O SRAM The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized as 32K words of 36 bits. It Features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q536 allows the user to perform transparent writes and data pass through. Two data bus ports are provided - a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 - D35), data output...