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MCM69R737A - 4M Late Write LVTTL

Datasheet Summary

Description

PBGA Pin Locations 4K 4L (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T 5L, 5G, 3G, 3L (a), (b), (c), (d) 4E 4M 4U 3U 5U

Features

  • rent (x18) (x36) Symbol VDD VDDQ IDD1 IDD2 ISB1 ISB2 ISB3 Min 3.15 3.15.
  • Typical.
  • 5.
  • 380 450 180 170 150 30 Typical.
  • 6.
  • 360 420 180 170 150 30 Typical.
  • 7.
  • 330 390 180 170 150 30 Typical.
  • 8.
  • 320 370 180 170 150 30 Max 3.6 3.6 480 550 250 250 230 50 Unit V V mA mA mA mA mA 5 6,.

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Datasheet Details

Part number MCM69R737A
Manufacturer Motorola
File Size 212.42 KB
Description 4M Late Write LVTTL
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69R737A/D Advance Information 4M Late Write LVTTL The MCM69R737A/819A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R819A organized as 256K words by 18 bits, and the MCM69R737A organized as 128K words by 36 bits wide are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered.
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