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MCM69R738A - 4M Late Write 2.5 V I/O

General Description

PBGA Pin Locations 4K 4L (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T 5L, 5G, 3G, 3L (a), (b), (c), (d) 4E 4M 4U 3U 5U

Key Features

  • ISB1 ISB2 Min 3.15 2.3.
  • Typical.
  • 5.
  • 390 450 180 170 150 Typical.
  • 6.
  • 360 420 180 170 150 Typical.
  • 7.
  • 330 390 180 170 150 Typical.
  • 8.
  • 320 370 180 170 150 Max 3.6 2.7 490 550 250 250 230 Unit V V mA mA mA mA 5 6, 10 7 8, 10 Notes Sleep Mode Power Supply Current ISB3.
  • 30 30 30 30 50 mA 9, 10.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

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MCM69R736A 4M Late Write HSTL
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MCM69R820A 4M Late Write 2.5V I/O

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69R738A/D Advance Information 4M Late Write 2.5 V I/O The MCM69R738A/820A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R820A organized as 256K words by 18 bits, and the MCM69R738A organized as 128K words by 36 bits wide are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered.