MPC8260A - Micro Processor

Section 1.6, “Ordering Information” Page 3 7 7 12 12 13 19 19 22 29 42 44 PRELIMINARY

Table 1 shows the functionality that defines each derivative of the HiP4-enhanced PowerQUICC II family.

Table 1.

• rocessor.
• System core microprocessor supporting frequencies of 150.
• 300 MHz.
• Separate 16-Kbyte data and instruction caches:.
• Four-way set associative.
• Physically addressed.
• LRU replacement algorithm.
• PowerPC architecture-compliant memory management unit (MMU).
• Common on-chip processor (COP) test interface.
• High-performance (6.6.
• 7.65 SPEC95 benchmark at 300 MHz; 420 Dhrystones MIPS at 300 MHz).
• Support.