Description
Section 1.6, “PLL Configurations” Section 1.7, “System Design Information” Section 1.8, “Document Revision History” Section 1.9, “Ordering Information” Page 1 3 5 5 27 34 35 45 49
To locate any published errata or updates for this document, refer to the website at http://www.motorola.com/semicondu
Features
- erface.
- Programmable timing supporting either FPM DRAM, EDO DRAM, or SDRAM.
- High-bandwidth bus (32- or 64-bit data bus) to DRAM.
- Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices.
- Supports 1-Mbyte to 1-Gbyte DRAM memory.
- 16 Mbytes of ROM space.
- 8-, 32-, or 64-bit ROM.
- Write buffering for PCI and processor accesses.
- Supports normal parity, read-modify-write (RMW), or ECC.
- Data-path buffering bet.
MPC8240EC Datasheet
