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MPC8255 Datasheet Mpc826xa (hip4) Family Hardware Specifications

Manufacturer: Motorola Semiconductor (now NXP Semiconductors)

Overview: www.DataSheet4U.com Freescale Semiconductor, Inc. Advance Information MPC8255TS/D Rev. 2.2, 10/2001 MPC8255 PowerQUICC ™ II Technical Summary Freescale Semiconductor, Inc... The MPC8255 PowerQUICC II™ is a versatile communications processor that integrates a high-performance RISC microprocessor that implements the PowerPC architecture, a flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The MPC8255 is a Footprint-compatible, lower-cost version of the MPC8260. The core is an embedded variant of the 603e microprocessor, referred to as the G2 core, with 16 Kbytes of instruction cache, 16 Kbytes of data cache, and a floating-point unit (FPU). The system interface unit (SIU) consists of a flexible memory controller that interfaces to almost any user-defined memory system (and many other peripherals), making this device a complete system on a chip. The communications processor module (CPM) includes all the peripherals found in the MPC860, with the addition of two high-performance communications channels that support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet). The MPC8255 has dedicated hardware that can handle up to 128 full-duplex, time-division-multiplexed logical channels. This document describes the functional operation of the MPC8255, with an emphasis on peripheral functions. Additional information about this microprocessor can be found in the MPC603e RISC Microprocessors User’s Manual (order number: MPC603EUM/AD). 1.

Key Features

  • integer core.
  • A core version of the MPC603e microprocessor.
  • System core microprocessor supporting frequencies of 150.
  • 200 MHz.
  • Separate 16-Kbyte data and instruction caches:.
  • Four-way set associative.
  • Physically addressed.
  • LRU replacement algorithm.
  • PowerPC architecture-compliant memory management unit (MMU).
  • Common on-chip processor (COP) test interface.
  • High-performance (4.4.
  • 5.1 SPEC95 benchmark at.

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