MTB33N10E Datasheet PDF - Motorola TMOS POWER FET Specs

MTB33N10E - TMOS POWER FET

Datasheet Summary

Features

t specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electr.

Datasheet Details

Part number	MTB33N10E
Manufacturer	Motorola
File Size	266.16 KB
Description	TMOS POWER FET
Datasheet	MTB33N10E Datasheet
Additional preview pages of the MTB33N10E datasheet.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTB33N10E/D ™ Data Sheet TMOS E-FET.™ High Energy Power FET D2PAK for Surface Mount Designer's MTB33N10E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time.

Published: Sep 13, 2005 |