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MTP75N03HDL - TMOS POWER FET

Key Features

  • VGS 16 12 8 4 0 70 20 28 24 10000 TJ = 25°C ID = 75 A VDD = 15 V VGS = 5 V VDS , DRAIN.
  • TO.
  • SOURCE.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP75N03HDL/D Advanced Information HDTMOS E-FET ™ High Density Power FET N–Channel Enhancement–Mode Silicon Gate This advanced high–cell density HDTMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low–voltage, high–speed switching applications in power supplies, converters and PWM motor controls, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs www.DataSheet4U.com where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients.