UPD17015
Overview
- 17K architecture Program memory (ROM) Data memory (RAM) General-purpose I/O ports
- LCD controller/driver
- Clock generator port : General registers : 3K bytes (1528 × 16 bits) : 97 × 4 bits : 12 : 9 segments × 4 commons Minimum required peripheral hardware is built into the chip.
- PLL frequency synthesizer and 220-MHz (MAX.) prescaler
- Low-voltage operation
