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UPD2118-2 - 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY

Download the UPD2118-2 datasheet PDF. This datasheet also covers the UPD2118 variant, as both devices belong to the same 16384 x 1 bit dynamic mos random access memory family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Single+5VSupply,±10%Tolerance.
  • Low Power: 138 mW Max Operating 16 mW Max Standby.
  • Low VDD Current Transients.
  • All Inputs, Including Clocks, TTL Compatible.
  • Non.
  • Latched Output is Three.
  • State.
  • RAS.
  • Only.
  • Refresh.
  • 128 Refresh Cycles Required.
  • Page Mode Capability.
  • CAS Controlled Output Allows Hidden Refresh PIN IlPD2118 IlPD2118.
  • 2 IlPD2118.
  • 3 ACCESS TIME 150 ns 120 ns 100 r1'S RIW CYC.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPD2118-NEC.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NEC (now Renesas Electronics)

Part Number Description
UPD2118-3 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY
UPD2118 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY
UPD2114L 4K-Bit Static RAM
UPD2114L-1 4K-Bit Static RAM
UPD2114L-2 4K-Bit Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NEe Microcomputers, Inc. 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY NEe ,uPD2118 ,uPD2118-2 JI. PD2118-3 [~OO~[~~~~ffirnW DESCR IPTION ThepPD2118 is a single +5V power supply, 16384 word by 1 bit Dynamic MOS RAM. The IlPD2118 achieves high speed with low power dissipation by the use of single tran· sistor dynamic storage cell design and advanced dynamic circuitry. This circuit design results in the minimizing of current transients typical of dynamic RAMS. This in turn II results in high noise immunity of the IlPD2118 in a system environment. By using a multiplexing technique, the IlPD2118 can be packaged in an industry standard 16·Pin Dip utilizing 7 address input pins for the 14 address bits required. The two 7 bit address words are referred to as the ROWand COLUMN address.