Description
technology using full CMOS six-transistor memory cell.
Features
- 1.8 ± 0.1 V power supply and HSTL I/O.
- DLL circuitry for wide output data valid window and future frequency scaling.
- Separate independent read and write data ports with concurrent transactions.
- 100% bus utilization DDR READ and WRITE operation.
- Four-tick burst for reduced address frequency.
- Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
- Two output clocks (C and /C) for precise flight time and clock sk.
UPD44165084 Datasheet
