UPD44324364 Datasheet PDF - NEC 36M-BIT DDRII SRAM Specs

UPD44324364 - 36M-BIT DDRII SRAM

This page provides the datasheet information for the UPD44324364, a member of the UPD44324084 36M-BIT DDRII SRAM family.

Datasheet Summary

Description

The µPD44324084 is a 4,194,304-word by 8-bit, the µPD44324094 is a 4,194,304-word by 9-bit, the µPD44324184 is a 2,097,152-word by 18-bit and the µPD44324364 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

Features

1.8 ± 0.1 V power supply and HSTL I/O.
DLL circuitry for wide output data valid window and future frequency scaling.
Pipelined double data rate operation.
Common data input/output bus.
Four-tick burst for reduced address frequency.
Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving d.

Datasheet Details

Part number	UPD44324364
Manufacturer	NEC
File Size	368.75 KB
Description	36M-BIT DDRII SRAM
Datasheet	UPD44324364 Datasheet
Additional preview pages of the UPD44324364 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44324084, 44324094, 44324184, 44324364 36M-BIT DDRII SRAM 4-WORD BURST OPERATION Description The µPD44324084 is a 4,194,304-word by 8-bit, the µPD44324094 is a 4,194,304-word by 9-bit, the µPD44324184 is a 2,097,152-word by 18-bit and the µPD44324364 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44324084, µPD44324094, µPD44324184 and µPD44324364 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.

Published: Nov 25, 2006 |