UPD4482162 Overview
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 integrates unique synchronous peripheral circuitry, 2bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide...
UPD4482162 Key Features
- 3.3 V or 2.5 V core supply
- Synchronous operation
- Internally self-timed write control
- Burst read / write : Interleaved burst and linear burst sequence
- Fully registered inputs and outputs for pipelined operation
- Single-Cycle deselect timing
- All registers triggered off positive clock edge
- 3.3 V or 2.5 V LVTTL patible : All inputs and outputs
- Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
- Asynchronous output enable : /G