UPD485505 - LINE BUFFER

Product Overview

NEC

Part number	UPD485505
Manufacturer	NEC
File Size	174.30 KB
Description	LINE BUFFER
Datasheet	UPD485505 Datasheet
Additional preview pages of the UPD485505 datasheet.

The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer.

Its CMOS static circuitry provides high speed access and low power consumption.

The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers.

5,048 words by 8 bits.
Asynchronous read/write operations available.
Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns) 15 to 5,048 bits (Cycle time: 35 ns).
Power supply voltage VCC = 5.0 V ± 0.5 V.
Suitable for sampling one line of A3 size paper (16 dots/mm).
All input/output TTL compatible.
3-state output.
Full static operation; data hold time = infinity Ordering Information Part Number R/W Cycle Time 25 n.

📁 Similar Datasheet

UPD48011318 - Low Latency DRAM (Renesas)
UPD48011336 - Low Latency DRAM (Renesas)
UPD482234 - (UPD482234 / UPD482235) 2M-Bit Dual Port Graphics Buffer (NEC Electronics)
UPD482235 - (UPD482234 / UPD482235) 2M-Bit Dual Port Graphics Buffer (NEC Electronics)
UPD488588 - 288M bits Direct Rambus DRAM (Elpida Memory)
UPD488588FF-C80-40 - 288M bits Direct Rambus DRAM (Elpida Memory)
UPD4066B - Quad Analog Switch / Miltiplexer (ETC)
UPD41256 - 262144 Dynamic NMOS RAM (NEC Electronics)

Other Datasheets by NEC

Published: Nov 12, 2005 |