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UPD485506 - LINE BUFFER

General Description

The µPD485506 is a high speed FIFO (First In First Out) line buffer.

Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits.

Its CMOS static circuitry provides high speed access and low power consumption.

Key Features

  • 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode).
  • Asynchronous read/write operations available.
  • Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns) 15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns).
  • Power supply voltage VCC = 5.0 V ± 0.5 V.
  • Suitable for sampling two lines of A3 size paper (16 dots/mm).
  • All input/output TTL compatible.
  • 3-state output.
  • Full static operation;.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DATA SHEET MOS INTEGRATED CIRCUIT µPD485506 LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT Description The µPD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power consumption. The µPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the µPD485506 can execute read and write operations independently on an asynchronous basis. Thus the µPD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are four versions, E, K, P, X and L.