S7N401831M Overview
The S7N403631M and S7N401831M are 4,718,592-bits Synchronous Static SRAMs. The NTSRAM, or Non-Turnaround Static Random Access Memory utilizes all the bandwidth in any bination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock.
S7N401831M Key Features
- Fully registered inputs and outputs for pipelined operation
- VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply
- VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or
- Byte Writable Function
- Enable clock and suspend operation
- Single Read/Write control pin
- Asynchronous output enable control
- Self-timed Write control
- Three Chip Enable for simple depth expansion with no data
- An interleaved burst or a linear burst mode