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NTE74LS78 Integrated Circuit TTL − Dual J−K Flip−Flop with Preset, Common Clock and Common Clear
Description: The NTE74LS78 is a dual J−K flip−flop in a 14−Lead plastic DIP type package that contains two negative−edge−triggered flip−flops with individual J−K, preset inputs, and common clock and common clear inputs. The logic levels at the J and K inputs may be allowed to change while the clock pulse is high and the flip−flop will perform according to the function table as long as minimum setup and hold times are observed. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.
Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . .
NTE74LS78 Datasheet
