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74ABT16841A - 20-bit bus interface latch

General Description

The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs.

Key Features

  • High speed parallel latches.
  • Live insertion/extraction permitted.
  • Extra data width for wide address/data paths or buses carrying parity.
  • Power-up 3-State.
  • Power-up reset.
  • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors.
  • Output capability: +64 mA /.
  • 32 mA.
  • Latch-up protection exceeds 500 mA per Jedec Std 17.
  • ESD protection exceeds 2000 V per MIL STD 883 Method.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ABT16841A 20-bit bus interface latch (3-State) Product data Replaces data sheet 74ABT16841A/74ABTH16841A of 2002 Dec 17 2004 Feb 02 Philips Semiconductors Philips Semiconductors 20-bit bus interface latch (3-State) Product data 74ABT16841A FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying parity • Power-up 3-State • Power-up reset • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors • Output capability: +64 mA / –32 mA • Latch-up protection exceeds 500 mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model DESCRIPTION The 74ABT16841A Bus interface latch is designed to prov