74ALS161B Overview
Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B).
74ALS161B Key Features
- D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requir
- Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous c
- Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold ti
- Synchronous counting and loading
- Two count enable inputs for n-bit cascading
- Positive edge-triggered clock
- Asynchronous reset (74ALS161B)
- Synchronous reset (74ALS163B)
- High speed synchronous expansion
- Typical count rate of 140MHz