Datasheet4U Logo Datasheet4U.com

74LVC594A - 8-bit shift register

General Description

The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage register.

Separate clock and reset inputs are provided on both shift and storage registers.

The input can be driven from either 3.3 V or 5 V devices.

Key Features

  • s s s s s s s s 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard JESD8-B/JESD36 ESD protection: x HBM JESD22-A114-D exceeds 2000 V x CDM JESD22-C101-C exceeds 1000 V s Specified from.
  • 40 °C to +85 °C and.
  • 40 °C to +125 °C. 3.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74LVC594A 8-bit shift register nexperia
74LVC594A-Q100 8-bit shift register nexperia
74LVC595A 8-bit serial-in/serial-out or parallel-out shift register NXP Semiconductors
74LVC595A 8-bit serial-in/serial-out or parallel-out shift register nexperia
74LVC540A OCTAL BUFFER/LINE DRIVER Diodes

Other Datasheets by NXP Semiconductors

Part Number Description
74LVC541A Octal buffer/line driver
74LVC543A Octal D-type registered transceiver
74LVC544A Octal D-type registered transceiver
74LVC573A Octal D-type transparent latch
74LVC574A Octal D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com 74LVC594A 8-bit shift register with output register Rev. 01 — 24 May 2007 Product data sheet 1. General description The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes.