Datasheet4U Logo Datasheet4U.com

74LVC594A-Q100 - 8-bit shift register

General Description

The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register.

Separate clock and reset inputs are provided on both shift and storage registers.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power dissipation.
  • Direct interface with TTL levels.
  • IOFF circuitry provides partial Power-down mode operation.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger action.
  • Co.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74LVC594A 8-bit shift register NXP
74LVC595A 8-bit serial-in/serial-out or parallel-out shift register NXP Semiconductors
74LVC540A OCTAL BUFFER/LINE DRIVER Diodes
74LVC540A Low-Voltage CMOS Octal Buffer ON Semiconductor
74LVC541A Octal buffer/line driver NXP

Other Datasheets by Nexperia

Part Number Description
74LVC594A 8-bit shift register
74LVC595A 8-bit serial-in/serial-out or parallel-out shift register
74LVC541A Octal buffer/line driver
74LVC541A-Q100 Octal buffer/line driver
74LVC573A Octal D-type transparent latch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC594A-Q100 8-bit shift register with output register Rev. 3 — 3 September 2020 Product data sheet 1. General description The 74LVC594A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The device features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.