74LVT2952 Datasheet PDF (3.3V LVT octal registered transceiver)

74LVT2952 - 3.3V LVT octal registered transceiver

Description

The 74LVT2952 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.

This device combines low static and dynamic power dissipation with high speed and high output drive.

The 74LVT2952 device is an 8-bit registered transceiver.

Features

8-bit registered transceiver.
Independent registers for A and B buses.
Input and output interface capability to systems at 5 V supply.
TTL input and output switching levels.
Output capability: +64 mA/32 mA.
Latch-up protection exceeds 500 mA per JESD78 class II level A.
ESD protection:.
HBM JESD22-A114E exceeds 2000 V.
MM JESD22-A115-A exceeds 200 V.
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs.

Datasheet Details

Part number	74LVT2952
Manufacturer	NXP
File Size	535.66 KB
Description	3.3V LVT octal registered transceiver
Datasheet	74LVT2952 Datasheet
Additional preview pages of the 74LVT2952 datasheet.

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Full PDF Text Transcription

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74LVT2952 3.3 V Octal registered transceiver; 3-State Rev. 4 — 11 September 2013 Product data sheet 1. General description The 74LVT2952 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT2952 device is an 8-bit registered transceiver. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPxx) if the clock enable (CExx) is LOW. The data is then present at the 3-state output buffers, but is only accessible when the output enable (OExx)) is LOW. Data flow from An inputs to Bn outputs is the same as for Bn inputs to An outputs.

Published: Oct 5, 2005 |