AV16821DL Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74ALVT16821 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) Product specification Supersedes data of 1997 May 01 IC24 Data Handbook 1998 Feb 13 Philips Semiconductors Philips Semiconductors Product specification 2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ALVT16821 Features - 20-bit positive-edge triggered register - 5V I/O patible - Multiple VCC and GND pins minimize switching noise - Live insertion/extraction permitted - Power-up reset - Power-up 3-State - Output capability: +64m A/-32m A - Latch-up protection exceeds 500m A per Jedec Std 17 - ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The 74ALVT16821 high-performance Bi CMOS device bines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O patibility to 5V. The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (n CP) and Output Enable (n OE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (n OE) controls all ten 3-State buffers independent of the register operation. When n OE is Low, the data in the register appears at the outputs. When n OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. - Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs QUICK REFERENCE DATA SYMBOL t PLH t PHL CIN COUT ICCZ PARAMETER Propagation delay n CP to n Q Input capacitance Output...