AV16823DL Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS 74ALVT16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State) Product specification Supersedes data of 1998 Mar 03 IC23 Data Handbook 1998 Jun 12 Philips Semiconductors Philips Semiconductors Product specification 2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 74ALVT16823 Features - Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ALVT16823 has two 9-bit wide buffered registers with Clock Enable (n CE) and Master Reset (n MR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. It is designed for VCC operation from 2.5 V to 3.0 V with I/O patibility to 5 V. - 5V I/O patible - Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors - Live insertion/extraction permitted - Power-up 3-State - Power-up Reset - No bus current loading when output is tied to 5 V bus - Output capability: +64m A/- 32m A - Latch-up protection exceeds 500m A per Jedec Std 17 - ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model - Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs QUICK REFERENCE DATA SYMBOL t PLH t PHL CIN COUT ICCZ PARAMETER Propagation delay n CP to n Qx Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50p F VI = 0V or VCC VI/O = 0V or 3.0V Outputs disabled TYPICAL UNIT 2.5V 2.5 3 9 40 3.3V 1.9 3 9 70 ns p F p F µA ORDERING INFORMATION PACKAGES 56-Pin Plastic SSOP Type...