BST100 Datasheet | NXP Semiconductors

DISCRETE SEMICONDUCTORS DATA SHEET BST100 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DESCRIPTION P-channel vertical D-MOS transistor TO-92 variant envelope and intended for use in relay, high-speed and line-transformer drivers. Features - Very low RDS(on) - Direct interface to C-MOS - High-speed switching - No second breakdown QUICK REFERENCE DATA Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance - ID = 200 m A; - VGS = 10 V Transfer admittance - ID = 200 m A; - VDS = 15 V PINNING - TO-92 VARIANT 1 2 3 = source = gate = drain  Yfs typ. RDS(on) - VDS ±VGSO - ID Ptot BST100 max. max. max. max. typ. max. 60 V 20 V 0.3 A 1 W 4,5 Ω 6 Ω 200 m S PIN CONFIGURATION handbook, halfpage d 2 3 g MAM144 s Note: various pinout configurations available. Fig.1 Simplified outline and symbol. April 1995 Philips Semiconductors Product...