BST122 Datasheet | NXP Semiconductors

DISCRETE SEMICONDUCTORS DATA SHEET BST122 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DESCRIPTION P-channel vertical D-MOS transistor in SOT89 envelope and intended for use in relay, high-speed and line-transformer drivers, using SMD-technology. Features - Very low RDS(on) - Direct interface to C-MOS, TTL - High-speed switching - No second breakdown QUICK REFERENCE DATA Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance - ID = 200 m A; - VGS = 10 V Transfer admittance - ID = 200 m A; - VDS = 15 V PINNING - SOT89 1 2 3 = source = drain = gate  Yfs typ. RDS(on) - VDS ±VGSO - ID Ptot BST122 max. max. max. max. max. typ. 60 V 20 V 0,25 A 1 W 10 Ω 7.5 Ω 125 m S PIN CONFIGURATION handbook, halfpage d g 1 Bottom view 2 3 MAM354 s Marking: LN Fig.1 Simplified outline and symbol. April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS...