BST120 Datasheet | NXP Semiconductors

DISCRETE SEMICONDUCTORS DATA SHEET BST120 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DESCRIPTION P-channel vertical D-MOS transistor in SOT89 envelope and intended for use in relay, high-speed and line-transformer drivers, using SMD technology. Features - Very low RDS(on) - Direct interface to C-MOS - High-speed switching - No second breakdown QUICK REFERENCE DATA Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance - ID = 200 m A; - VGS = 10 V Transfer admittance - ID = 200 m A; - VDS = 15 V PINNING - SOT89 1 = source 2 = drain 3 = gate  Yfs typ. RDS(on) - VDS ±VGSO - ID Ptot BST120 max. max. max. max. typ. max. 60 V 20 V 0,3 A 1 W 4,5 Ω 6 Ω 200 m S PIN CONFIGURATION handbook, halfpage d g 1 Bottom view 2 3 MAM354 s marking: LM Fig.1 Simplified outline and symbol. April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note 1. Transistor mounted on ceramic substrate: area = 2,5 cm2 and thickness = 0,7 mm. Rth j-a...