BUK9830-30 Datasheet | NXP Semiconductors

DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using ’trench’ technology, the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2k V. It is intended for use in automotive and general purpose switching applications. QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Tsp = 25 ˚C Drain current (DC) Tamb = 25 ˚C Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 30 12.8 5.9 8.3 150 30 UNIT V A A W ˚C mΩ PINNING - SOT223 PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION PIN CONFIGURATION SYMBOL d g s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 100 ˚C Tamb = 100 ˚C Tsp = 25 ˚C Tamb = 25 ˚C Tsp = 25 ˚C Tamb = 25 ˚C MIN. - 55 MAX. 30 30 10 12.8 5.9 9 4.1 51 23.6 8.3 1.8 150 UNIT V V V A A A A A A W W ˚C THERMAL RESISTANCES SYMBOL Rth j-sp Rth j-amb PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS Mounted on any PCB Mounted on PCB of Fig.19 TYP. 12 MAX. 15 70 UNIT K/W K/W December 1997 Rev 1.100 Philips Semiconductors Product specification Trench MOS™ transistor Logic level FET ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 p F, 1.5 kΩ) MIN. - BUK9830-30 MAX. 2 UNIT k V STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS ±V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage...